Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms with large coarse-grained blocks and datapath-style (bus-based) interconnect. While papers on CGRAs stretch back to the 1990s, and with recent commercial CGRAs introduced by several companies, a modelling and exploration framework for CGRA architectures has been lacking. CGRA-ME is a software framework under active development at the University of Toronto that allows a human architect to specify a hypothetical CGRA architecture using an XML-based language or a C++ API. A set of benchmark applications can be mapped into the modelled CGRA to assess its area and performance. Verilog RTL for the CGRA can be automatically generated for verification by simulation, or for synthesis with an FPGA or standard-cell ASIC flow. CGRA-ME provides an open-source platform enabling research on CGRA architectures and CAD algorithms.