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Jobs Posted on the Whova Community Board of 2022 International Symposium on Computer Architecture

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Postdocs, Researchers & PhDs in Security | OS | Prefetching | Core-CPU | FPGAs | SAT solvers | Simulation & Modeling
National University of Singapore (NUS)
We are currently looking for outstanding researchers to complement our computer architecture research group at the National University of Singapore (NUS). Experience in, but not limited to, one or more the following areas is preferred (recent research linked via square brackets):

* Side-channel security (both microarchitecture and physical) [1,2,3,4]
* OS HW/SW optimization
* Prefetching [2]
* Core CPU design [5,6]
* FPGA acceleration
* SAT solver acceleration
* Simulation/modeling [7,8]

Feel free to email me directly, and let's chat at ISCA this year.

We are currently prioritizing Postdoc and PhD candidates. We are also open to working with excellent researchers at any level (B.S. / M.S / Interns).

[1] USENIX Security 2022 "Elasticlave: An Efficient Memory Model for Enclaves," https://www.usenix.org/conference/usenixsecurity22/presentation/yu-jason
[2] https://arxiv.org/abs/2109.00474 "Leaking Control Flow Information via the Hardware Prefetcher"
[3] "Sentry-NoC: A Statically Scheduled NoC for Secure SoCs," NOCS 2021, https://ieeexplore.ieee.org/abstract/document/9634866
[4] "Laser Attack Benchmark Suite," ICCAD 2021, https://ieeexplore.ieee.org/abstract/document/9256786
[5] "NOREBA: A Compiler-Informed Non-speculative Out-of-Order Commit Processor," ASPLOS 2021 http://dx.doi.org/10.1145/3445814.3446726
[6] "Efficient Instruction Scheduling Using Real-time Load Delay Tracking", https://arxiv.org/abs/2109.03112
[7] "LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications," HPCA 2022, https://doi.org/10.1109/HPCA53966.2022.00051
[8] "BarrierPoint: Sampled Simulation of Multi-threaded Applications," ISPASS 2014, http://dx.doi.org/10.1109/ISPASS.2014.6844456

Link: https://comp.nus.edu.sg/~tcarlson
Core Team , IC & System Architecture
Xscape Photonics
Opportunity to join as the first employee and core team member of a pre-Series A funded silicon Photonics startup. The candidate would own the IC technology strategy and execution. The role would be an individual contributor role that would morph into a leadership and management position as the individual builds the team. Preferred experience in analog IC and interface design for silicon Photonics systems
SoC performance architect/modeling engineer
MediaTek
In this role, you will be a member of the System-on-Chip (SoC) platform modeling team, working with architecture, silicon and software engineering teams to shape the architecture of MediaTek's future SoCs. The position calls for independent performance modeling and analysis, documentation, and collaboration with teams across MediaTek. We are looking for highly motivated, hands-on individuals who are passionate about performance modeling of sophisticated SoC features in C++/Python to demonstrate their value and impact.
Link: https://careers.mediatek.com/eREC/JobSearch/JobDetail/MTK120220316008?langKey=en-US
Software Engineer - SoC Performance Analysis
Google
Performance Analysis and modeling of advanced SoC Features.
Link: https://careers.google.com/jobs/results/120055394379670214-software-engineer-iii-soc-performance-analysis/?company=Google&company=Google%20Fiber&company=YouTube&employment_type=FULL_TIME&gclid=CjwKCAjw77WVBhBuEiwAJ-YoJOA5VqF3ofSCGJBlaSl70A5QbWy3IyH5-s2Gg71Tj1qM-V4dijtwCxoC0HcQAvD_BwE&gclsrc=aw.ds&hl=en_US&jlo=en_US&location=United%20States&q=software%20engineer%20soc%20performance%20analysis&sort_by=relevance&src=Online%2FHouse%20Ads%2FBKWS
SoC Memory Performance Architect
Apple
In this role, you will be a member of the Platform Architecture team, working with hardware and software engineering groups to shape the architecture of Apple’s future System-on-Chips (SoC). We are seeking an energetic and highly motivated SoC performance engineer to drive development of our memory controllers and system caches for the next-generation of Apple silicons.

Link: https://jobs.apple.com/en-us/details/200143653/soc-memory-performance-architect
CPU/memory researchers and technical managers
AMD Research
AMD Research is hiring! We are looking for talented CPU and/or memory researchers across multiple experience levels. We also have technical manager positions. Talk to me to find out why we love what we do at AMD Research!

You can also send your resume to me at Yasuko.Eckert@amd.com.
Link: https://jobs.amd.com/search/?createNewAlert=false&q=AMDRESEARCH%20not%20co-op&locationsearch=
Systems Performance, Efficiency, Architecture
Google
The Systems and Services Infrastructure Performance team at Google develops the methodology for the high performance architecture and design of all systems deployed in Google data centers (servers, storage, networking, machine learning systems based on TPUs, and transcoding accelerators, etc.). We are expanding our world class team that fearlessly addresses the engineering challenges of architecting, designing, and developing systems at planetary scale. Many of the problems we work on require invention, since the existing state of the art is not sufficient. Although we do not always publish our inventions, you can find some of our work in the top Systems and Machine Learning conferences, and our research.google website (https://research.google/teams/system-performance/).

Some new initiatives that we are looking to staff are on:
- Google SoC modeling: goo.gle/position-soc-perf
- ML for Systems Efficiency: goo.gle/position-hwsw-codesign
- Planet-scale Database Acceleration: goo.gle/position-hwsw-codesign - Segment Optimized Computing: goo.gle/position-hwsw-codesign
Link: http://goo.gle/sys-confs
Several positions available: SW eng, ML deployment eng, Perf optimization, perf modeling
Cruise, LLC
Cruise, the self-driving car company that is transforming transportation in the cities we love, is looking for new graduates as well as senior engineers for several positions including generic software engineers, ML deployment engineers, performance optimization, and engineers with performance modeling skill set.
Please email your resume to amin.farmahini@getcruise.com. Amin Farmahini is attending the conference as well, so please feel free to connect to him or ask any questions you may have.
Follow us on twitter @Cruise or visit https://getcruise.com/
PhD/Postdoc in compilers for Sw-Hw co-design
University of Murcia
This project focuses on compile-time program analysis, customization, and optimization to enable novel hardware optimizations. In particular, we will analyze the program’s control-flow and data-flow and detect memory accessing patterns both in the compiler’s middle-end and back-end. Static information will be conveyed from software to hardware to reduce hardware complexity and eliminate redundant runtime analyses.

The PhD student / Postdoc is expected to collaborate closely with computer architects that will leverage the static analysis to design hardware optimizations. Candidates should have a Master Degree / PhD degree, respectively, in Computer Science, Computer Engineering, or equivalent.

Candidates must have taken courses in the following areas: compilers, computer architecture, parallel programming. The candidate must clearly document a high degree of self-motivation in the application. In addition, the applicant must be able to work well in a diverse group, comfortable giving and receiving constructive criticism, and have strong abilities for critical thinking and structured work. These competencies are as important as the technical qualifications.

The PhD / postdoc position is for a maximum of four / two years and optionally includes up to 60 / 80 teaching hours per academic year. Excellent skills in spoken and written English are required.

Application: The application must include a statement (at most 2 pages) of the applicant’s motivation for applying for this positions. The application must include a CV, degrees and grades, a copy of the MSc / PhD thesis, publications (and specific descriptions of the candidate’s own contributions), and the earliest possible starting date. At least one letter of recommendation and contact information for references should be provided. For applying to it, please send a mail to aros@ditec.um.es and alexandra.jimborean@um.es
Link: https://www.hipeac.net/jobs/13318/phdpostdoc-in-compilers-for-software-hardware-co-design/
Multiple open positions in Microsoft Azure Hardware Architecture team
Microsoft
Azure Hardware Architecture (AHA) has multiple open positions in hardware architecture, hardware security, hardware verification, firmware and more!

Check out our open positions by visiting https://aka.ms/ahajobs
or reach out to ahacomms@microsoft.com
Link: https://aka.ms/ahajobs
Postdoc and Research Staff
University of Chicago
Large-scale novel graph analytics architecture and system software. Help pioneer a new approach that scales to 1000s of nodes.
Link: https://drive.google.com/file/d/1ejrbchrYV-tskZ6wfBvk3r82WfSRORsc/view?usp=sharing
ML Architecture Codesign and Performance
Google
The Core Machine Learning (ML) team at Google is the central machine learning platform team that provides ML software tools and hardware infrastructure to all the Google product areas. The ML Performance team is responsible for enabling and extracting maximum efficiency from Google's ML resources.

We push state-of-the-art performance techniques for Google’s production and research ML workloads, perform hardware-software codesign to inform future TPU architecture, develop comprehensive performance, numerical and debugging infrastructure and tools, and establish industry-wide benchmarking and Google's performance leadership through MLPerf. We collaborate closely across the hardware-software stack in our efforts -- with ML researchers, hardware designers, and compiler/runtime engineers.
Pre-Silicon Software Modelling Engineer
AMD
- Work with internal and external customers to help debug problems running their workloads on the models.
- Develop test plans and tests' functionality of the models.
- Develop high-performance functional models for AMD SoCs and platform.
- Improve functionality, stability, and performance of existing models.
- Develop new, innovative debug features.
- Work closely with architecture teams to understand and model new designs.
Link: https://jobs.amd.com/job/Austin-SOC-Virtual-Design-Methodology-Engineer-147141-Texa/865405900/
Computer Scientist 3
Pacific Northwest National Laboratory
The Data Sciences & Machine Intelligence group in the Advanced Computing, Mathematics, and Data Division at PNNL seeks a multifaceted Computer Scientist to join the group to lead and support scientific research in the broad areas of data science, machine intelligence, and autonomous learning and reasoning. This is an excellent opportunity to hone and develop your scientific career at an outstanding research institution by joining an interdisciplinary research team that focuses on accelerating scientific discovery.

The primary emphasis of this position will be to design and develop complex analytic workflows, benchmarks and mini-apps for the evaluation of novel data science systems. You will build computational models of the workflows and assist system architects and computer engineer co-design and evaluate hardware and software system proposals. The candidate will contribute to the areas of Network Science, Machine Learning and Artificial Intelligence System Design, and Benchmarking. A successful candidate should have expertise in one or more of the following technical areas: network science and graph analytics, optimization and optimization-based decision making, artificial intelligence and machine learning, performance studies, and benchmarking.

Preferred Skillsets:
Proficient in programming High Performance Computing Systems and in analyzing performance and scalability of algorithms on such systems
Good understanding of HPC system software and how to manage resources on distributed heterogenous systems
Experience in implementing and designing Machine Learning algorithms to solve scientific problems. Of particular interest are learning algorithms in distributed or federated settings
Experience in evaluating algorithms robustness and predict their failures

Link: https://careers.pnnl.gov/jobs/4234?lang=en-us
postdoc position @uva
University of Virginia
Join cs@uva to conduct research in the areas of computer systems and architecture broadly defined, especially relating to data movement and resource management in the context of emerging memory technologies, near-data processing, and hardware accelerators.
Link: https://engineering.virginia.edu/departments/computer-science/about-computer-science/cs-employment
Multiple open positions in the Advanced Architecture Development Group (AADG) Intel
Intel
The Advanced Architecture Development Group (AADG) at Intel is building a future-generation CPU core that will deliver leadership core performance. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. If you are excited about breakthrough technologies for future-generation CPU cores, we invite you to join us, do something wonderful! Check out the link to see open positions.
Link: https://jobs.intel.com/page/show/search-results#q=AADG
Machine Learning Accelerator Architect / Accelerator Architect
Waymo
Waymo is hiring! Come join us in our pioneering efforts to bring self-driving cars on the road. Come and flex your talents as computer architects to design computers that drive cars!
Link: waymo.com/joinus/3988451/ waymo.com/joinus/3979060/
graph analytics researcher or simulator developer or software engineer
Intel Corporation
multiple positions in the US or Europe
PhD position in Hardware Security
ETH Zurich
See the link below.
Link: https://www.jobs.ethz.ch/job/view/JOPG_ethz_kpCFrpddIrSX0T67Jc
PhD position in Systems Security
ETH Zurich
See the link below.
Link: https://www.jobs.ethz.ch/job/view/JOPG_ethz_Uw3bZOX3PX9WWdktoH
Postdoctoral researcher in computer security
ETH Zurich
The computer security group (COMSEC) at the Department of Electrical Engineering and Information Technology at ETH Zurich is looking for a postdoctrol researcher in the area of computer security.

We consider applicants with experience in publishing in top computer architecture, computer systems and security venues. The candidate is expected to establish their own research profile in the group while contributing to the education activities and supervision of the projects.
Link: https://comsec.ethz.ch/join/
Postdoc in Datacenter Architecture & Systems
UC Santa Cruz
I am looking for a Postdoc interested in working in processor microarchitecture, datacenters, and compilers in sunny California. Check out my website and talk to me at the conference.
Link: https://people.ucsc.edu/~hlitz/
PhD position in Computer Architecture
NTNU - Norwegian University of Science and Technology
We are regularly looking for talented individuals who like to work hard, dig deep, and influence tomorrow's computing technologies. If you are one of them and want to join our team, please contact us

About the position

We have a vacant PhD position at the Department of Computer Science (IDI), NTNU, Norway with a research focus on computer architecture. The computing landscape is shifting from the traditional desktop computing to mobile-cloud computing model. In this new model, datacenters have emerged as the workhorses that do all the heavy-duty computations and serve as the backbone of mobile services. A modern datacenter draws multi mega-watts of power and costs over $100 million to deploy. However, the processors deployed in datacenters remain highly under-utilized due to a large mismatch in application characteristics and processor microarchitecture.

The objective of this PhD project is to specialize server processor architectures to match application characteristics. Datacenter applications are characterized by massive instruction footprints that frequently stall the core front-end. TailorMade will investigate low overhead instruction delivery mechanisms to mitigate this front-end bottleneck. Datacenter applications offer very limited instruction- and memory-level parallelism which causes core back-end to burn energy on instructions without much performance gain. TailorMade will investigate allocating expensive resources only to performance critical instructions while executing the rest cheaply.
Link: https://folk.ntnu.no/rakeshk/join-us.html
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