Hardware in R&D
Jump Trading
Tons of projects and problems to solve at Jump
Link:
None
FPGA Logic Designer
Algo-Logic Systems, Inc
Algo-Logic Systems is hiring FPGA logic designers to implement IP cores and applications for electronic trading, data center object store, and other hardware-accelerated network applications. Algo-Logic's IP cores are currently deployed in systems that require ultra low-latency Ethernet, TCP/IP networking, and/or associative lookup. You should be ready and able to design, develop, and deploy logic on devices from Xilinx and Intel on multiple card platforms.
Link:
https://www.algo-logic.com/fpga-logic-designer
FPGA Design and Design Verification Opportunities!
BAE Systems
Are you an FPGA Design or FPGA Design Verification Engineer with 2 to 20+ years of experience looking for the next step to grow your career? Do you want to design technology leading products that really matter and be a part of a cause greater than yourself? Then, help us Protect Those Who Protect Us® by developing Next Generation Electronic Systems Products and Solutions. Our employees work on the world’s most advanced electronics – from saving emissions in the City of Lights to powering the Mars Rover to protecting the F-35 fighter jet. We need your talent, motivation, and vision to join our team. BAE Systems has recently been awarded exciting new programs and is currently undergoing significant growth. We have numerous positions in Southern New Hampshire, New Jersey, Austin/Dallas Texas, Manassas VA, Greenlawn NY, Endicott NY, Los Angeles CA, Fort Wayne IN, and Plymouth/Burlington Massachusetts in facilities located in those areas.
Link:
https://jobs.baesystems.com/global/en/job/81055BR/Senior-Level-FPGA-Design-Verification-Engineers-All-Levels
Research and Software Engineer
AMD-Xilinx
Open source emphasis and embedded research topics across AMD-Xilinx platforms.
Link:
https://jobs.amd.com/job/Longmont-MTS-Research-&-Software-Engineer-Colo/874722200/
Internship Positions
Lattice Semiconductor Corp.
A few internship positions are still available: including one in the architecture organization:
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• Knowledge in Verilog, System Verilog, Perl, TCL, Python, UVM
• Help evaluate and define next-generation FPGA fabric
• Help with FPGA architecture modeling, evaluation and competitive benchmarking
• Develop, setup and run scripts in Python or equivalent
• Work closely with senior members from architecture and other organizations to generate, analyze and review the evaluation results.
Link:
https://recruiting2.ultipro.com/LAT1001LATT/JobBoard/e7f50c7c-43f9-46e9-86ed-b31eaa369842/OpportunityDetail?opportunityId=6faa37cb-b206-4522-aff6-633deb2e3ec1
FPGA Programmer
Parkyeri
You will work as a PGA designer/programmer, editing existing and designing new digital electronic logic circuits as well as creating and implementing designs for Altera and/or Xilinx Field Programmable Gate Arrays. Your tasks will include, but not limited to the following:
Designing, developing and editing digital electronic circuits
Defining and coordinating interfaces within the systems
Interface FPGAs with I/O, mermory and storage peripherals
Develop and carry out hardware tests
Requirements for application*:
Cover Letter: Please detail how your previous experiences relate to the description of the internship.
Written Essay/Description: Describe briefly one hardware design you have edited/created (a git repository link would be a plus) in the past. Please elaborate on the challanges you faced during the development.
*Applicants without these two requirements will be rejected.
Work will be tailored according to the capabilities and career growth potential of the candidate as well as company requirements.
Link:
https://erasmusintern.org/traineeship/fpga-programmer-remote-1
FPGA Design, Verification, and Hardware Security Research Engineer
Georgia Tech Research Institute (GTRI)
Available positions include full-time, MS/PhD graduate research assistant, intern, and co-op.
The Georgia Tech Research Institute (GTRI) Trusted Microelectronics Program Office (TMPO) researches tools and techniques to evaluate the security, trust, and reliability of FPGAs, ASICs, SoCs, microcontrollers, and other microelectronics devices as well as the critical systems which rely upon them.
Responsibilities range from CAD/EDA tools development, semiconductor device design, fabrication, and verification, to clean-room equipment utilization. Formal methods and other advanced algorithmic techniques will be leveraged to enable and evaluate security and trustworthiness pre- and post-fabrication.
Full-time employees are Research Faculty of Georgia Tech and have the opportunity for dual appointments and teaching positions with other departments of the university. TMPO is a division of GTRI's cyber security lab which contains 300+ engineers and scientists and represents >10% of the total research award funding at Georgia Tech.
Link:
https://careers.gtri.gatech.edu/en-us/job/497509/fpgaasic-design-and-hardware-security-research-engineercipher
Postdoctoral Research Fellow Positions
KAUST
Multiple Postdoc openings are available at KAUST, Saudi Arabia, as part of the launch of the new Accelerated Connected Computing Lab (ACCL) in the Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division (https://cemse.kaust.edu.sa). KAUST is a postgraduate-only research university on the shores of the Red Sea, just one hour from Jeddah International Airport. Postdocs enjoy generous salaries and free accommodation and healthcare on a world class campus with ample recreational facilities and a private beach. KAUST offers you the opportunity to pursue world-class research among a highly diverse student/postdoc population of high achievers, and interaction with world-leading faculty across a range of disciplines.
Applicants with expertise in the following areas are sought:
- FPGAs for Networking Applications
- Coarse Grained Reconfigurable Arrays and Overlay architectures
- Virtualisation of interfacing and memory for FPGA accelerators
If you want to live on the shores of the Red Sea, with guaranteed sunshine year round, while pursuing world-leading research, with unparalleled access to hardware resources and networking opportunities, please reach out.
Link:
https://cemse.kaust.edu.as/accl
1 PhD and 1 Postdoc positions on Hardware Security of AI Accelerators
CentraleSupélec, IETR Lab
We have two positions (PhD & Postdoc) to work in the project ATTILA, funded by the ANR (French national research agency). The topic is on physical (power/EM) Side-Channel Analysis (SCA) vulnerabilities of DNN hardware accelerators built using Approximate Computing (AxC) in heterogeneous, reconfigurable platforms (SoC/MPSoC-FPGAs).
The specific direction of each position will be decided in accordance with and based on the experience of both persons. Main tasks involve: (1) study SCA vulnerabilities of DNN accelerators built using AxC and investigate the impact on leakage behaviour and SCA resistance; (2) Design Space Exploration of approximate solutions trading-off SCA resistance with inference quality; (3) investigate dynamic, run-time countermeasures leveraging AxC and lightweight AI to hide/mask side-channel leakage.
More information on the provided link or in HiPEAC jobs portal: https://www.hipeac.net/jobs/13319/1-phd-and-1-postdoc-positions-on-hardware-security-of-ai-accelerators/
Link:
https://www.ietr.fr/securing-dnn-hardware-accelerators-against-side-channel-attacks-phd
PhD positions at ETH Zurich
ETH Zurich
Multiple fully-funded PhD positions in EDA and reconfigurable computing are available at ETH Zurich, Switzerland.
We are interested in developing a broad scope of high-level synthesis techniques to ease the programmability of digital hardware (e.g., FPGAs). Our goal is to bridge the gap between software and hardware by developing language abstractions, compiler flows, and hardware devices that enable software developers from different domains to accelerate emerging compute-intensive applications.
For more details about the positions and to apply, please visit the link below or reach out by email.
https://jobs.ethz.ch/job/view/JOPG_ethz_w0JHXmQTFDqLuBX8EV
Link:
https://sites.google.com/view/lanajosipovic
1 Postdoc position on Custom Hardware Accelerators for Homomorphic Encryption
University of Washington Bothell
We have one postdoc position on Homomorphic Encryption Hardware. This position is a full-time one-year appointment. It is supported by an NSF Grant “Custom Hardware Accelerators for Privacy-Preserving Image Processing”.
Main duties and responsibilities are:
* Design, develop, and test FPGA-based hardware accelerators of homomorphic encryption primitives.
* Publish research results in peer-reviewed journals and/or FPGA-related conference proceedings.
If you have any questions about this position, please email at sunwoong@uw.edu.
Link:
https://ap.washington.edu/ahr/position-details/?job_id=89618
Senior Staff CPU Research Scientist
Futurewei
Responsibilities:
• Lead research in the next generation microprocessor, SOC, heterogenous system design
• Architecture and performance study in CPU pipeline, micro-architecture, timing and PPA
• Work with micro-architect to define and evaluate various micro-architecture solutions
• Analyze benchmark and typical application workload, optimize system level performance.
• Knowledge about compiler, be able to research software hardware co-design and collaborate with application software team.
• Parallel program, high performance computing and GPGPU
• IC Design methodology and design space exploration
• Publish paper and patent from research results
Requirement:
• Must hold a Ph.D. in Computer Science/Engineering, Electrical Engineering, or a related field with at least 4 years of relevant research experience.
• Excellent knowledge of microprocessor design including ISA, architecture, compiler, firmware Deep understanding in memory subsystem, cache coherent, cache coherent interconnect.
• Outstanding track record in research and publication.
• Excellent communication skills.
Link:
https://phf.tbe.taleo.net/phf01/ats/careers/v2/viewRequisition?org=FUTUREWEITECH&cws=47&rid=11026
Senior Staff Engineer, CPU Micro architect/Design
Futurewei Technologies, Inc.
We are looking for Senior Staff Engineer - CPU Micro architect/ Design. The candidate will take part in definition and implementation of Futurewei’s next generation microprocessor project. The individual shall be responsible for one or more phases of the development.
Depending on the actual assignment and skill set, the candidate will focus on one or more parts of the technical areas below:
•Define the next generation micro-architecture, participate in Timing Feasibility studies, Cost and power estimation, Performance projection, Competitive analysis
•Participate in RTL design and write optimized RTL code for high-speed timing, area and power
•Lead the development effort and carry out design work of critical function units
•Be able to conduct microprocessor research, publish papers.
Qualifications:
•Hands-on experience in CPU architecture/micro-architecture/design
•Experience in Instruction fetch, rename/decode, out of order design, execution.
•Must be a highly organized, detail-oriented self-starter, who can deliver independently as well as in a team environment
•Master’s degree or higher preferred
•Good verbal and written communication skills
Link:
https://phf.tbe.taleo.net/phf01/ats/careers/v2/viewRequisition?org=FUTUREWEITECH&cws=47&rid=11027
Senior Staff CPU Performance Engineer
Futurewei Technologies, Inc.
Depending on the actual assignment and skill set, the candidate will focus on all or part of the technical areas below:
•Conducting performance analysis to identify performance bottlenecks and come up with improvement solution
•Porting and developing various open-source and proprietary tools
•Porting and developing various open-source and commercial CPU workloads
•Coding, testing, and debugging various microarchitecture components such as vector-processing, load-store and data-prefetch units, to name a few
Qualifications/Requirements:
•Strong C++ , Python script and object-oriented programming skills – API programming is a plus
•Familiarity with the Linux environment
•Experience in workload generation using open-source compilers and tools – RISC-V is a plus
•Basic understanding of ISA and Assembly code – RISC-V is a plus
•Hands-on experience in CPU architecture/microarchitecture simulators – GEM5 is a plus
•Basic understanding of computer architecture and microarchitecture, including out-of-order execution, memory system and pipeline design
•Must be a highly organized, detail-oriented self-starter, who can deliver independently as well as in a team environment
•Master’s degree or higher preferred
•Good verbal and written communication skills
Link:
https://phf.tbe.taleo.net/phf01/ats/careers/v2/viewRequisition?org=FUTUREWEITECH&cws=47&rid=11068
